Semi Doped
- Episódios
- 59
- Publicação
- semanal
- Último episódio
- 12 nov 2026
Sobre o podcast
The business and technology of semiconductors. Alpha for engineers and investors alike.
Participantes
- Austin LyonsApresentação
- Vikram SekarApresentação
Episódios 59
Jensen Huang Resigns
Jensen Huang resigned as Nvidia CEO this morning, and Austin and Vik recorded two hours after the news broke. They argue that a board must prioritize corporate integrity over short-term shareholder value, even …
Notas do episódio
Jensen Huang resigned as Nvidia CEO this morning, and Austin and Vik recorded two hours after the news broke. They argue that a board must prioritize corporate integrity over short-term shareholder value, even for a legendary founder. The discussion then turns to Nvidia's critical lack of a succession plan and the long-term risk of the company's unique, founder-led culture decaying into bureaucracy.
Presented by Crusoe: Fine-tune and serve open models without managing a single GPU. Deploy on Crusoe in one click, or download and run it anywhere. Upload a dataset, pick an open model, and pay per token rather than per GPU hour. Accounts are free, and get $5 in credit when you sign up. Try Serverless Fine-Tuning: https://semidoped.com/crusoe
Key Takeaways:
- A board's first duty is governance, not shareholder value. Even a founder CEO must be forced out for breaking company rules, because keeping them sends a message that lying and rule-breaking are acceptable.
- The hardest job demands the highest standard. The immense pressure of being Nvidia's CEO is the reason for strict conduct rules, not an excuse for leniency.
- Nvidia has no succession plan — Ian Buck is the only plausible internal CEO candidate. Unlike competitors, Nvidia's 'all Jensen, all the time' media strategy has left its leadership bench visibly thin.
- Jensen's unique management style is the biggest succession risk. His flat structure with ~60 direct reports is impossible for a successor to replicate, creating a vacuum that invites bureaucracy.
- The real long-term risk is Nvidia decaying into a spreadsheet-CEO culture. The fear is a slide into the managerial, process-driven leadership that hampered competitors like Intel.
- A leadership crisis at Nvidia is AMD's opportunity to attack. For a competitor like Lisa Su, Nvidia's moment of weakness is the time to 'put my foot on the gas,' not switch teams.
- Arm CEO Rene Haas is a credible external successor. As an Nvidia alumnus, he understands the culture but also brings proven CEO experience from a different silicon leader.
This episode is supported by Meter. You have the GPUs and the power. Now who builds the network, and who do you call when it breaks? Meter designs, deploys, and runs frontend, storage, and management networks on its own switches and its own network OS. One call reaches the team that designed the hardware and wrote the software. https://semidoped.com/meter
Chapters:
0:00 Introduction
0:23 The News Flash
4:12 Why the Board Had to Act
9:43 Shareholder Value vs. Integrity
14:05 The Pressures of the CEO Role
15:08 The Highest Standard
15:57 Short-Term Stability
19:08 Long-Term Risk: Bureaucracy
19:24 Founder vs. Professional CEO
22:38 Candidate: Lisa Su
26:50 Candidate: Rene Haas
28:14 Candidate: Ian BuckFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/Intel's Earnings Disaster: Bad Luck, Bad Planning, or Both?
Intel just had its worst day on the stock market in 55 years, with shares falling nearly 30%. But here's the strange part: Intel actually reported a strong quarter. Revenue grew, its data center business …
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Intel just had its worst day on the stock market in 55 years, with shares falling nearly 30%. But here's the strange part: Intel actually reported a strong quarter. Revenue grew, its data center business surged, and the company beat expectations. So what went wrong?
In this episode of Semi Doped, Vik Sekar and Austin Lyons dig into Intel's Q3 2026 earnings and the problems behind its disappointing outlook.
Three issues are at the center of Intel's troubles: a weakening PC market driven by rising memory prices, a shortage of advanced packaging substrates that limits server CPU production, and a tragic factory accident in Israel that disrupted chiplet supply.
But how much of this was bad luck, and how much was poor planning?
We debate whether Intel should have anticipated the surge in demand for server CPUs from agentic AI, whether its manufacturing strategy can respond quickly enough, and what these problems mean for its ambitions to become a leading-edge foundry alternative to TSMC.
We also step back to examine what Intel's experience tells us about the broader semiconductor market.
Topics covered:
- Why Intel's stock crashed despite strong earnings
- How the AI memory boom is hurting the PC market
- Why substrate shortages are constraining server CPU production
- The consequences of Intel's Fab 28 accident
- Whether Intel misjudged demand for agentic AI CPUs
- Intel 18A, 14A, and the long-term foundry opportunity
- Why strong demand doesn't necessarily translate into revenue
- Why investors are increasingly demanding returns from the AI infrastructure buildout
The bigger question: Is Intel facing a temporary supply-chain problem, or are its troubles a warning sign for the broader AI semiconductor industry?
Presented by Crusoe: Fine-tune and serve open models without managing a single GPU. When we sat down with Crusoe’s product team, Austin asked: what will you do with my data? Their answer: They don’t touch or see it. Your training data is encrypted so even Crusoe’s own admins can’t see it, and the fine-tuned model is yours. Deploy on Crusoe in one click, or download and run it anywhere. Upload a dataset, pick an open model, and pay per token rather than per GPU hour. Run a few versions, compare them, and download the one that works best. Accounts are free, and get $5 in credit when you sign up. Try Serverless Fine-Tuning: https://semidoped.com/crusoe
This episode is supported by Meter. You have the GPUs and the power. Now who builds the network, and who do you call when it breaks? Meter designs, deploys, and runs frontend, storage, and management networks on its own switches and its own network OS. One call reaches the team that designed the hardware and wrote the software. https://semidoped.com/meter
Chapters:
0:00 Intel's 35% Stock Drop
1:22 The Pre-Earnings Bull Case
4:03 Reason 1: Weak PC Market
12:25 The Flawed Q2 Pivot Plan
17:17 The IDM Model's Failure
20:23 Reason 2: Substrate Bottleneck
23:18 Chiplet Design's Fragility
25:18 Reason 3: The Fab 28 Explosion
40:46 The GPU Intelligence Gap
45:51 The Foundry Thesis Question
50:22 Packaging as a Hope Story
51:19 Four Lessons from the MeltdownFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/3D Stacked DRAM for Inference: d-Matrix's Sudeep Bhoja
The fundamental physics of data movement are forcing a shift to new memory architectures for AI inference. Sudeep Bhoja, co-founder and CTO of d-Matrix, joins Vik to detail the company's journey from a …
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The fundamental physics of data movement are forcing a shift to new memory architectures for AI inference. Sudeep Bhoja, co-founder and CTO of d-Matrix, joins Vik to detail the company's journey from a non-consensus bet on memory-bound inference to a full-rack 3D-stacked DRAM solution. Sudeep explains the pivot from analog to digital in-memory compute, the system-level disaggregation strategies for their Corsair card, and how the next-generation Raptor chip integrates with Nvidia's ecosystem.
"Essentially, we got 16 times the capacity of SRAM, while we retained SRAM bandwidth."
— Sudeep Bhoja, d-MatrixPresented by Crusoe: Fine-tune and serve open models without managing a single GPU. When we sat down with Crusoe’s product team, Austin asked: what will you do with my data? Their answer: They don’t touch or see it. Your training data is encrypted so even Crusoe’s own admins can’t see it, and the fine-tuned model is yours. Deploy on Crusoe in one click, or download and run it anywhere. Upload a dataset, pick an open model, and pay per token rather than per GPU hour. Run a few versions, compare them, and download the one that works best. Accounts are free, and get $5 in credit when you sign up. Try Serverless Fine-Tuning: https://semidoped.com/crusoe
Key Takeaways:
- The core problem in AI inference is a 1000x energy gap. Compute costs femtojoules per operation, but moving data from memory costs picojoules per bit.
- d-Matrix's first analog in-memory compute chip failed because it couldn't maintain 32-bit accumulation precision, forcing a pivot to a digital architecture.
- The Corsair card's digital in-memory compute delivers 150 TB/s of on-chip SRAM bandwidth — over 8x more than an Nvidia Blackwell GPU's 18 TB/s HBM.
- The next-gen Raptor chip stacks a logic die on a DRAM die, delivering 16x the capacity (32 GB) of the prior SRAM design while retaining ~100 TB/s bandwidth.
- This 3D stacking is over 10x more energy-efficient than HBM4, consuming just 0.37 pJ/bit versus an estimated 5 pJ/bit for an HBM4-plus-GPU system.
- Choosing the stacking order is a 'pick your poison' trade-off. d-Matrix put logic-on-top for better thermals, accepting a harder power delivery challenge through the DRAM.
- The go-to-market product is a full rack with 144 Raptor packages, aggregating 2.3 TB of high-bandwidth memory designed to drop into Nvidia's VR rack infrastructure.
This episode is supported by Meter. You have the GPUs and the power. Now who builds the network, and who do you call when it breaks? Meter designs, deploys, and runs frontend, storage, and management networks on its own switches and its own network OS. One call reaches the team that designed the hardware and wrote the software. https://semidoped.com/meter
Chapters:
0:00 Intro: The Cost of a Token
3:28 The 2019 Bet on Inference
7:43 Nighthawk: Analog In-Memory Compute
12:08 Why Analog Failed
19:02 Corsair: Digital In-Memory Compute
26:04 System Strategy: Speculative Decoding
37:05 Raptor: 3D Stacked DRAM
39:40 The 'Free Lunch' of 3D Stacking
45:00 Trade-off: Logic-on-Top vs DRAM-on-Top
54:14 Go-to-Market: The Nvidia VR Rack
1:03:17 The Future: Lightning & 4-High Stacks
1:12:45 The End State of InferenceFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/Why Marvell Wants Lumentum: Vertical Integration in AI Optics With Cignal AI
Marvell's potential acquisition of Lumentum is a strategic vertical integration play to capture the massive value optical components now unlock in the AI era. Andrew Schmitt and Scott Wilkinson of market …
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Marvell's potential acquisition of Lumentum is a strategic vertical integration play to capture the massive value optical components now unlock in the AI era. Andrew Schmitt and Scott Wilkinson of market research firm Signal AI join Austin and Vik to break down the deal's core drivers. They explain how Marvell could run the 'Broadcom playbook' by bundling DSPs and optics, even at the cost of competing with its own customers, and why Lumentum's future-facing assets like Optical Circuit Switches (OCS) and high-power lasers are just as critical as its current-gen transceivers.
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- The deal's driver is vertical integration, not securing laser capacity. Marvell wants to control the supply chain from chips to optics to co-design superior products for the fast-moving AI market.
- The economics have flipped. Optics margins have doubled from ~25% to nearly 50%, making them attractive for chipmakers to acquire — even if it means Marvell pays 20-30x what it might have cost years ago.
- Lumentum's real moat is manufacturing scale. While others can build a hundred 'unicorn' devices like 200G EMLs, Lumentum's advantage is its ability to produce them reliably by the million.
- The acquisition creates channel conflict. Marvell's DSP customers will now have to compete with a vertically integrated Marvell-Lumentum, a dynamic that has already pushed some players out of the coherent market.
- This is also a bet on future architectures. The deal secures Lumentum's critical assets for next-gen data centers, including Optical Circuit Switches (OCS) and high-power lasers for CPO and NPO.
- Lumentum has the capacity to do both. After a 4x expansion of its Indium Phosphide fab, it can supply a vertically integrated Marvell and continue selling lasers to the open market.
- A bidding war is likely. The guests speculate the news leak was intentional to attract other suitors like Nvidia, who could run the same vertical integration playbook.
Chapters:
0:00 Intro: Marvell & Lumentum
7:38 The Vertical Integration Driver
9:17 The Channel Conflict Problem
14:58 Transceiver Value Chain
17:38 Why Would Lumentum Sell?
21:23 Lumentum's InP Capacity
24:52 The Cost of Waiting
27:00 Manufacturing Scale Is the Moat
31:30 How AI Changed Component Value
33:43 CPO: The Integration Endgame
36:50 The 'Broadcom Playbook'
38:58 Prediction: A Bidding WarFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/Chapters:
0:00 Intro: Marvell & Lumentum
7:38 The Vertical Integration Driver
9:17 The Channel Conflict Problem
14:58 Transceiver Value Chain
17:38 Why Would Lumentum Sell?
21:23 Lumentum's InP Capacity
24:52 The Cost of Waiting
27:00 Manufacturing Scale Is the Moat
31:30 How AI Changed Component Value
33:43 CPO: The Integration Endgame
36:50 The 'Broadcom Playbook'
38:58 Prediction: A Bidding WarFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan
Intel's EMIB technology represents a scalable, cost-effective advanced packaging solution that now serves as a core strategic differentiator for its foundry services. Ravi Mahajan, a distinguished engineer …
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Intel's EMIB technology represents a scalable, cost-effective advanced packaging solution that now serves as a core strategic differentiator for its foundry services. Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality. They discuss the principle behind EMIB, interconnect where you need it and only where you need it: small silicon bridges carry the fine-pitch die-to-die signals, while the organic substrate's thick metal still delivers power and everything else. They also cover its manufacturing advantages over CoWoS and Intel's forward-looking roadmap for active bridges and top-side optics.
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
"When first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that."
— Ravi Mahajan, Intel FoundryKey Takeaways:
- EMIB was invented to outpace organic packages, whose wire escape density at the die edge improved only about 10% per generation. The principle Ravi keeps returning to is interconnect where you need it and only where you need it: fine-pitch silicon in small local patches at the die edges, with the organic substrate's thick metal still carrying power and everything else. Fine wires are a poor way to deliver power anyway, and small bridges cut from a wafer keep the silicon cost down.
- Bringing EMIB from concept to production required the convergence of five distinct technologies, including a custom 4-layer silicon process and handling dies half the thickness of an A4 sheet of paper.
- Intel strategically chose HBM as EMIB's first driver, betting that if it could solve for the highest-performance memory interconnect, the technology could then "waterfall down" to all other less demanding applications.
- EMIB's advantage over CoWoS is manufacturing scale. Silicon only where you need it means small bridges instead of a full-sized silicon interposer, avoiding its high cost and poor wafer utilization, which is critical for large, multi-reticle AI packages.
- The EMIB portfolio was planned from the start. The original patent included EMIB-T, which uses TSVs to solve the "torturous" power delivery path of routing power around the bridge instead of through it.
- EMIB is an Intel Foundry exclusive. Packaging dies from other foundries is logistically straightforward, positioning advanced packaging as a key strategic differentiator for Intel's services.
- Intel's future roadmap includes top-side optics, using the top surface of the package for optical I/O to complement the electrical I/O on the bottom, dramatically increasing total package bandwidth.
Chapters:
0:00 Intro: Ravi Mahajan
1:44 Pathfinding & The HIR Roadmap
7:58 The Two Drivers of EMIB
15:15 Decoupling I/O and Power
16:27 The 'Science Fiction' of EMIB
20:36 HBM as the Killer App
25:06 EMIB vs. CoWoS
31:44 Chiplets, UCIe, and Packaging Tiers
34:08 The EMIB Portfolio: T, M, Active
37:01 An Intel Foundry Exclusive
41:21 AI's Role in Packaging
43:26 Future: Top-Side OpticsMentioned in this episode:
- NEW EPISODE: Synopsys’s Amazon Deal and GPT-Synopsys: Ravi Subramanian (Semi Doped episode): https://daily.semidoped.com/p/new-episode-synopsys-will-take-a
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/RF Over Plastic Is a Third Option Between Copper and Optics: Point2's Sean Park
A novel third option is emerging for data center interconnects between short-reach copper and power-hungry optics. Point2 CEO Sean Park joins Vik Sekar to explain his company's Active RF Cable (ARC) …
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A novel third option is emerging for data center interconnects between short-reach copper and power-hungry optics. Point2 CEO Sean Park joins Vik Sekar to explain his company's Active RF Cable (ARC) technology, which sends high-frequency radio signals over a flexible plastic waveguide. Park details how this approach targets the critical 5-10 meter "scale-up" problem for AI clusters, claiming significant advantages in cable density, power efficiency, and latency over existing solutions.
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
"The bandwidth limitation simply comes from the existence of electrons. And this plastic, it doesn't have electron. So, in terms of bandwidth, it is unlimited. Bandwidth is unlimited. So, once our silicon works, we don't have to really change the this cable at all. Just scale the silicon, then it will it will be used for higher data rate."
— Sean Park, Point2 TechnologyKey Takeaways:
- The interconnect choice is no longer just copper vs. optics. Point2's Active RF Cable (ARC) creates a third category, sending 100-200 GHz signals over a plastic waveguide for the 5-10 meter reach AI scale-up requires.
- The core density advantage is 4x over copper. ARC uses a single plastic core instead of a differential pair (2x gain), then sends two channels per core using frequency division multiplexing (another 2x gain).
- The power savings come from silicon simplicity. By avoiding the laser, DSP, and TIA of optical modules, a 1.6T ARC module consumes <10 watts (~5 pJ/bit), with a roadmap to <2 pJ/bit for co-packaged versions.
- The latency improvement is three orders of magnitude. Because it requires no DSP, ARC latency is in the sub-nanosecond range — 1,000x better than DSP-based optical solutions, which is critical for all-reduce operations.
- The cable itself has a clear scaling path that copper lacks. A plastic waveguide is a dielectric with theoretically unlimited bandwidth, free of the skin effect that limits copper. Future speed gains will come from silicon shrinks alone.
- Practicality in the rack is a key feature. The flexible plastic cable has a 4.7 mm bend radius, tight enough to wrap around a finger, making it easier to route in dense chassis than fragile optical fiber.
Chapters:
0:00 Intro: RF Over Plastic
3:06 The Third Option
8:27 Investor Validation
13:20 How E-Tube Works
15:16 The 4x Density Advantage
18:28 Inside the OSFP Module
29:51 4.7mm Bend Radius
34:20 Roadmap to Co-Packaging
36:09 The No-Gearbox Advantage
42:00 Biggest Challenges
49:57 The Physics of Scaling
51:00 Origin Story: Wallpaper TVMentioned in this episode:
- Plastic Cables for AI Clusters: Can Point2’s E-Tube Disrupt Copper and Optics? (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/plastic-cables-for-ai-clusters-etube
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Austin Lyons and Vik Sekar host a micro-explainer on the two competing micro-emitter technologies for AI interconnects: microLEDs and microVCSELs. They break down Credo's surprising pivot at OCP from its …
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Austin Lyons and Vik Sekar host a micro-explainer on the two competing micro-emitter technologies for AI interconnects: microLEDs and microVCSELs. They break down Credo's surprising pivot at OCP from its microLED acquisition to a microVCSEL product, revealing the core physics that give microVCSELs superior speed and reach. The episode establishes the technical reasons why the industry is converging on microVCSELs for the critical 5-50 meter gap in AI data centers.
This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- The new battleground for AI interconnects is the 5-50 meter "reach gap"—too long for copper cables limited to ~7 meters, but too short for expensive, supply-constrained InP long-reach optics.
- MicroLEDs are limited by physics to ~3-5 Gbps over 5 meters. Their broad light spectrum causes "chromatic dispersion," smearing the signal and creating a hard ceiling on speed and reach.
- To achieve high bandwidth, microLEDs require massive parallelism—bundling ~300 slow lanes to hit 1 Tbps—which introduces significant manufacturing complexity in coupling hundreds of fibers.
- MicroVCSELs solve this, hitting 50 Gbps+ over 50 meters. Their "stimulated emission" physics creates a narrow, focused beam that suffers less from dispersion, enabling 10x the speed and reach of microLEDs.
- The supply chain is a key advantage. MicroVCSELs use a mature Gallium Arsenide (GaAs) process on 8-inch wafers, shared with cell phones, giving them a cost and scale advantage over exotic InP optics.
- MicroLEDs' niche is extreme heat. Their Gallium Nitride (GaN) material is highly temperature-insensitive, making them a candidate for very short-reach, high-reliability optics inside a hot server tray.
Chapters:
0:00 The Credo Pivot
3:49 The Talk of OCP
8:13 The 5-50 Meter Reach Gap
12:52 How MicroLEDs Work
21:10 MicroLEDs' Parallelism Problem
22:55 How MicroVCSELs Work
26:57 MicroVCSEL Performance Specs
31:51 The Physics of VCSELs
33:35 The Market Chooses MicroVCSELs
35:45 MicroLEDs' Niche: Heat
38:16 Teasing Future InterviewsMentioned in this episode:
- PicoJool’s Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects (Semi Doped episode): https://daily.semidoped.com/p/picojools-al-yuen-the-case-for-gaas
- A MicroLED Field Trip to Avicena (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/a-microled-field-trip-to-avicena
- MicroLEDs vs. Lasers: The Linewidth Tradeoff (Vik's Newsletter, free): https://www.viksnewsletter.com/p/microleds-vs-lasers-the-linewidth-tradeoff
- Understanding Energy Bands in Semiconductors (Vik's Newsletter, free): https://www.viksnewsletter.com/p/energy-bands-in-semiconductors
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/AI Inference Is a Data Movement Problem: Microsoft's Saurabh Dighe on Maia 300
Microsoft's Maia 300 is a fully co-designed system, optimized to solve the memory-bound "data movement problem" of emerging agentic AI workloads. Saurabh Dighe, Corporate VP of Azure Hardware Systems at …
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Microsoft's Maia 300 is a fully co-designed system, optimized to solve the memory-bound "data movement problem" of emerging agentic AI workloads.
Saurabh Dighe, Corporate VP of Azure Hardware Systems at Microsoft, sits down with Austin to detail the architecture, from its TSMC N2P chiplet design enabling 18 TB/s of HBM4 memory bandwidth to its use of AI agents for automated kernel optimization.
They discuss how this full-stack approach aims to maximize intelligence per watt and per dollar for Microsoft's planet-scale services.
This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe
Key Takeaways:
- Microsoft views AI inference as a data movement problem, not a compute problem. The energy cost of moving data to feed the compute engine can be two orders of magnitude higher than the compute itself.
- The design of Maia 300 is driven by the shift from chat to agentic AI, which creates memory-bound workloads. The system delivers a 7x token throughput increase per rack over Maia 200, with a 5x increase in rack-level memory bandwidth.
- Maia 300 uses a chiplet architecture to "extend the shoreline" of its single TSMC N2P compute die. This allows it to accommodate eight HBM4 stacks, delivering 18 TB/s of memory bandwidth.
- Microsoft is using AI agents for "agentic kernel optimization" to automate the creation of low-level software. This strategy aims to bypass the manual optimization bottleneck and enable "Day-zero model availability" for new AI models.
- The system is built for deployment flexibility. While servers use direct liquid cooling, a rack-level "heat exchanger unit" allows the 167 kW racks to be deployed in traditional air-cooled data centers.
- The network is a two-tiered scale-up fabric built on standard Ethernet. Copper connects the 96 accelerators within a rack, while optics connect racks into superpods of up to 12,288 accelerators.
Chapters:
0:00 Intro: Saurabh Dighe
1:39 Microsoft's Silicon Philosophy
5:52 Workload Shift: Agentic AI
9:32 The Data Movement Problem
14:20 Crusoe Ad Read
17:47 Maia 300 Specs
24:07 Chiplets & HBM4
29:12 Prefill/Decode Disaggregation
30:33 Two-Tiered Network
35:45 NPO vs. CPO
36:46 Rack-Scale Power & Cooling
41:35 Agentic Kernel Optimization
49:08 What's Next: Maia 400Follow Chipstrat:
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The demand for workload-specific hardware is forcing a strategic shift in the semiconductor IP business. Synopsys's Ravi Subramanian joins Austin to discuss why the company is moving to a new royalty-based …
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The demand for workload-specific hardware is forcing a strategic shift in the semiconductor IP business. Synopsys's Ravi Subramanian joins Austin to discuss why the company is moving to a new royalty-based model for its custom "application optimized IP," starting with a billion-dollar deal with Amazon. Ravi also unpacks Synopsys's partnership with OpenAI and its vision for AI "agent engineers" that augment human designers, while explaining why physics-based simulation remains the ultimate ground truth.
This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe
"in physics we trust is because at the end of the day, the ground truth to have the confidence, not hallucinate and be deterministic in your outcome is really what defines is a product going to be successful or not."
— Ravi Subramanian, SynopsysKey Takeaways:
- The hyperscaler IP model is shifting. Because 1-2 applications drive most revenue, companies like Amazon now demand custom “application optimized IP” instead of standards-based IP.
- Synopsys is adopting a new business model for this custom work: a license fee, a “customization fee” to prioritize scarce engineers, and for the first time, a royalty on the final chip.
- This new royalty model mirrors the Arm-Amazon partnership from a decade ago, aligning Synopsys with its customer’s 12-month design cycles and expanding its role to system-level bring-up.
- Synopsys’s AI strategy isn't just tools, but a new consumption model: customers can “hire” an AI agent engineer with a specific skillset, fitting directly into existing budgets and team structures.
- The GPT-Synopsys partnership with OpenAI is a turnkey service bundling a specialized LLM, the necessary compute, and forward-deployed engineers to solve the key adoption hurdles of model quality and compute scarcity.
- AI is for exploration, but physics is for verification. Accurately modeling a modern CFET requires 200x more device equations than a planar FET, a complexity that demands physics-based simulators as the ground truth.
Chapters:
0:00 Intro: The Amazon & OpenAI Deals
2:39 Application Optimized IP
6:04 The New Royalty Business Model
12:14 How Standard IP Differentiates
18:20 The Arm-Amazon Analogy
22:00 Synopsys's Role in Test Chips
26:06 The Three Stages of Chip Design
31:27 The 'Agent Engineer' AI Model
36:20 The GPT-Synopsys Partnership
39:27 In AI We Believe, In Physics We TrustFollow Chipstrat:
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The push to run AI agents on edge devices will not be driven by model labs or hardware vendors, but by service providers like Meta whose ad-based business models create a powerful financial incentive to offload …
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The push to run AI agents on edge devices will not be driven by model labs or hardware vendors, but by service providers like Meta whose ad-based business models create a powerful financial incentive to offload massive cloud compute costs onto the user's own powerful-but-idle hardware. Austin Lyons and Vik Sekar break down why the failed "AI PC" push has given way to a new, economically-driven strategy for on-device AI. They discuss how Qualcomm's acquisition of Modular provides the key software layer and why the ultimate vision is an "ecosystem of you" where the device acts as a context-aware orchestrator between local and cloud compute.
This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe
"[Model Labs] business model is we make money when we do inference in the cloud. And yet we are saying, actually, there's a world where we would really like to just run this stuff locally... Meta's like, bro, I want to help you at the edge."
— Austin Lyons, ChipstratKey Takeaways:
- The driver for edge AI is a business model conflict. Model labs like OpenAI sell cloud inference; service providers like Meta see it as a massive cost center for their ad-supported agents like Muse.
- Your phone is an underutilized edge server. Its specs—like 8GB of RAM and 2 vCPUs of power—are comparable to the dedicated cloud VMs that services like Meta's Muse provision for each user.
- The "AIPC" push failed because it was a hardware-first strategy without a use case. Today's edge AI push is a software-first strategy driven by the need to cut cloud OpEx for mass-market agents.
- The role of the edge device is becoming a "context translation layer." It uses private data like location and biometrics to intelligently decide which AI tasks run locally versus in the cloud.
- Qualcomm's acquisition of Modular is a key strategic move. It positions the open-source Mojo language as the "write once, run anywhere" software layer for deploying agents across diverse hardware.
- Personal agents will lead to the "end of apps." Fixed UIs, which force a designer's paradigm on the user, will be replaced by interfaces generated on demand via natural language.
- Google is missing its opportunity to lead in on-device AI. Despite vertical integration from TPUs to Pixel hardware and a leading ad business, it lacks the product execution of players like Meta.
Chapters:
0:00 Who Makes Local AI Happen?
1:25 Making the Intro with AI
4:43 Qualcomm's Agent Vision
6:54 Why AIPCs Failed
8:45 The Phone as a Portal
13:52 Meta's Incentive for Edge AI
24:05 The End of Apps & UIs?
32:31 The Ideal Personal Agent
34:25 The Edge as a Context Layer
38:17 Qualcomm's Modular Acquisition
43:16 The Ecosystem of You
48:01 Google's Missed OpportunityFollow Chipstrat:
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As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new …
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As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new standard by offering a low-cost, high-endurance alternative. Ilan details how ReRAM's simple back-end-of-line integration, automotive qualification, and future applications in AI in-memory compute create a compelling replacement for the incumbent technology.
"In geometries below 28 or 22 nanometer, flash reached its physical limit, actually. So physically you cannot implement embedded flash anymore and the industry had been looking for alternative technologies for a few decades now."
— Ilan Sever, WeeBit NanoKey Takeaways:
- The inflection point for on-chip memory is physical. Embedded flash cannot scale below the 28/22nm node because its floating gate becomes too small to reliably hold charge.
- The economic problem with eFlash is its 25-30% cost increase, a result of adding 8-10 extra masks to a standard CMOS process—a non-starter for cost-sensitive MCUs.
- ReRAM's manufacturing advantage is its simplicity. It's built in the back-end-of-line (BEOL) metal layers, adding only two masks and not interfering with the sensitive transistors below.
- The physics are different: ReRAM isn't storing charge, it's changing resistance by using voltage to form or dissolve a conductive filament of oxygen vacancies in a dielectric.
- Automotive qualification is the key market validation. WeeBit's ReRAM is qualified for the AEC-Q100 standard and demonstrates 100,000 write cycles—10x that of typical eFlash.
- The business model isn't just a recipe; it's a full IP module with the bit cell, analog circuits, digital logic, and programming algorithms, which is what SoC designers actually need.
- Beyond replacing flash, ReRAM (as a memristor) is a foundational technology for future in-memory compute (IMC) AI accelerators that perform calculations inside the memory to save power.
Chapters:
0:00 The Overlooked Memory
4:15 The eFlash Scaling Wall
6:03 Four Uses of NVM
23:19 The Cost of eFlash
27:29 Introducing ReRAM
32:25 How ReRAM Works
37:12 Fab-Friendly Materials
42:14 Automotive Qualification
44:30 The Vertically Integrated IP Model
51:13 Future: In-Memory Compute
54:19 Innovation Story: Self-TrimmingFollow Chipstrat:
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Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why …
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Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why they didn't build another me-too accelerator and instead placed a differentiating technical bet: High Bandwidth Compute (HBC).
The difference between HBC and HBM: HBM is stacked DRAM that shuttles data across wide buses to a separate accelerator — very high bandwidth, but expensive and power-hungry. HBC bonds stacked DRAM directly on top of a custom logic die using wafer-on-wafer techniques, so a lot of the compute runs literally next to memory. The result is lower latency and lower power per bit — and 18x effective bandwidth on the AI 250 versus the AI 200 at the SAME 768 GB LPDDR capacity and the SAME 160 kW per rack.
Why the late-mover bet works: Qualcomm's differentiation isn't just architectural. Their foundry and memory-vendor relationships let them credibly promise the multi-megawatt-to-gigawatt supply hyperscalers need. Memory vendors are developing their own HBC-equivalent variants as partners rather than pure competitors, and Qualcomm expects the two technologies to co-evolve. Silicon is back in the lab; proof points land in Q1/Q2 2027.
Chapters:
0:00 Introduction
2:49 The Memory Wall Problem
8:05 HBC Physical Architecture
9:33 HBC vs. Custom HBM
11:50 Silicon Proof Points Coming
12:08 Managing Thermals
13:34 Dragonfly AI 250
14:48 Trillion-Parameter Model on One Card
16:56 Tokenomics and TCO
18:26 Why TCO is Key
19:26 Manufacturing at ScaleFollow Chipstrat:
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The debate over "pacing" AI for safety is a red herring, as the practical outcome of more safety work is not a slowdown but a net increase in demand for compute hardware. Austin Lyons and Vik Sekar unpack Dario …
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The debate over "pacing" AI for safety is a red herring, as the practical outcome of more safety work is not a slowdown but a net increase in demand for compute hardware. Austin Lyons and Vik Sekar unpack Dario Amodei's call to slow down frontier AI development, arguing that the true governors on AI are not voluntary agreements but physical data center bottlenecks and geopolitical realities. They conclude that the push for more safety and interpretability will ultimately drive more sales of both training (GPUs) and inference (XPUs) hardware.
Today's sponsor is G2i — expert training data, evals, and RL environments for AI labs: https://fandf.co/4wZvKHS
Chapters:
0:00 Introduction: Pacing AI
1:36 Recapping Dario Amodei's Essay
7:42 Hot Take: Anthropic vs. OpenAI
11:34 The John Deere Playbook
15:22 The Problem with Interpretability
17:53 Pulling the Plug
19:03 The Real Bottleneck: Data Centers
22:03 The Geopolitical Blind Spot
23:41 Counter-narratives: Meta & Open Source
27:26 The Investment Thesis: Pacing Increases Compute
32:29 The Financial System Analogy
36:05 AI Safety as the New Cybersecurity
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The emergence of user-friendly AI agents is creating massive new hardware demand, which in turn is forcing the semiconductor industry into a complex, multi-year transition to High NA EUV lithography and an …
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The emergence of user-friendly AI agents is creating massive new hardware demand, which in turn is forcing the semiconductor industry into a complex, multi-year transition to High NA EUV lithography and an entirely new 12-inch photomask standard. Austin Lyons and Vik Sekar unpack the physics and economics of ASML's move to High NA, explaining why it necessitates a shift from 6-inch to 6x12-inch masks and what this means for the timelines of TSMC, Intel, and Samsung.
"This is where you have to get the whole supply chain coordinated around this. And this is why you really ultimately need ASML's biggest customers to stand up and say, 'We're going to buy this.'"
— Austin Lyons, ChipstratKey Takeaways:
- ASML's High NA EUV (0.55 NA) solves resolution but creates a new problem: anamorphic optics (4x by 8x demagnification) cut the exposure field in half, effectively doubling the cost per wafer.
- The industry's fix for High NA's halved output is a new 6x12-inch photomask standard — the 12-inch dimension compensates for the 8x demagnification, restoring the full 26mm x 33mm reticle size.
- This shift to 12-inch masks is a full supply chain problem, which is why TSMC is waiting until 2030 for high-volume manufacturing while the ecosystem matures over the next 5-7 years.
- Intel's aggressive first-mover strategy on High NA — with over 1 million wafers processed to date — is a direct reaction to its disastrous delay in adopting the previous generation of EUV.
- Nearly 30% of ASML's revenue comes from recurring services (€2.8B of €9B in Q2), giving it a more stable financial profile than a typical equipment manufacturer.
- The new wave of AI agents (Astra, Muse, Instinct) is moving from simple instruction-following to proactive partnership, creating hundreds of millions of new users for server CPUs and memory.
- Integrating AI agents into ubiquitous text platforms like WhatsApp is key for mass adoption, as it solves the 'blank text box problem' for non-technical users who can simply text a request.
Chapters:
0:00 Episode Opening
2:23 The Rise of AI Agents
6:00 Instinct: The Autonomous Agent
10:50 Productizing AI for Mass Adoption
14:03 From AI Agents to ASML
24:29 The Photomask Stitching Problem
31:49 High NA's Anamorphic Optics Tradeoff
36:39 The Cost of a Halved Reticle
37:26 The 6x12-Inch Mask Solution
39:08 A Full Supply Chain Problem
41:17 TSMC, Samsung & Intel Timelines
48:24 Intel's EUV History LessonFollow Chipstrat:
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Austin and Vik react to OpenAI's Jalapeño announcement at Hot Chips. Plus extra spicy questions like should OpenAI sell it, how much of this was AI-written RTL, and where is Anthropic's chip?Key …
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Austin and Vik react to OpenAI's Jalapeño announcement at Hot Chips. Plus extra spicy questions like should OpenAI sell it, how much of this was AI-written RTL, and where is Anthropic's chip?
Key Takeaways:- The chip's core design philosophy is "dark silicon is cheaper than idle accelerators" — using one balanced chip and power-gating unused blocks is more efficient than a two-chip (e.g. GPU + LPU) solution.
- The unprecedented nine-month RTL-to-tapeout cycle was enabled by AI for EDA tools, serving as a wake-up call that small, expert teams can now develop Rubin-class chips in under a year.
- Jalapeño's key innovation is a NUMA-style architecture that gives each accelerator a local HBM slice, solving the memory contention that throttles performance in unified memory systems.- OpenAI chose Broadcom's ESUN for its scale-up network to connect 128 chips in the rack at 600 GB/s and up to 2,048 chips across 16 racks at 200G --- all scale up!
- The design's "regret factor" principle justifies generality — the opportunity cost of being unable to support a future model is far higher than the marginal cost of adding hardware flexibility upfront.
Chapters:
0:00 Hot Chips Reaction
2:32 Designing for User Experience
11:16 A Generalized Inference Chip
14:18 The Foundry-IDM Analogy
18:42 The 'Regret Factor'
21:02 The 9-Month Design Cycle
23:45 Challenging the Two-Chip Solution
35:08 Solving HBM Underutilization
36:46 The NUMA Architecture Solution
39:28 System-Level ESUN Networking
42:06 Dark Silicon vs. Idle Accelerators
49:08 A Wake-Up Call for the Industry
52:59 Where's Anthropic's Chip?
Follow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/Grok Bots and How CPUs are used in Agentic AI
The rise of user-friendly agentic AI platforms will create a massive new demand category for dedicated, high-core-count "agentic CPUs" to execute tasks in parallel, fundamentally reshaping the server CPU market …
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The rise of user-friendly agentic AI platforms will create a massive new demand category for dedicated, high-core-count "agentic CPUs" to execute tasks in parallel, fundamentally reshaping the server CPU market beyond just feeding GPUs.
Key Takeaways:
- The 'Mac Mini Craze' wasn't about having a GPU on your desk — it was also about security, as users needed a sandboxed machine to run untrusted agent code like OpenClaw, a problem cloud VMs solve too.
- In AI servers, the GPU is the 'genius' doing the thinking, while the host CPU is the 'assistant' whose primary job is keeping the GPU fed, requiring high single-core performance.
- Agentic tasks create a 'spillover' of parallel work that overwhelms the host CPU, creating a new demand category for dedicated, high-core-count 'agentic CPUs' in separate racks.
- The procurement decision for agentic CPUs becomes about cost-per-core, or 'cost per employee' — balancing core count (like AMD's 256-core chips) against single-core speed.
- Intel's P-rack (Performance) and E-rack (Efficiency) offerings are a direct response to this need for heterogeneous CPU solutions tailored to different agentic workloads.
- The mass adoption of agentic AI could create demand for a billion new CPU cores in the cloud, driven by the convenience of 'easy button' platforms over self-hosting.
- A key bottleneck to this heterogeneous future is the orchestration software needed to schedule jobs across different CPUs and accelerators from multiple vendors.
Chapters:
0:00 Introducing Grok bot
3:45 Grok bot's Cloud VM Architecture
6:28 The 'Mac Mini Craze' Explained
14:38 Three CPU Deployment Models
16:02 GPU as Genius, CPU as Assistant
21:36 The Limits of the Host CPU
25:20 The 'Office Building' Analogy
29:09 Cost-Per-Core is the Metric
31:20 Intel's P-rack and E-rack
37:32 The Orchestration Bottleneck
40:19 Where Grok bot's VM Lives
44:22 The Unanswered QuestionFollow Chipstrat:
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Tensordyne co-founder and CPO R K Anand joins Austin to discuss the company's strategy for disrupting AI inference. RK explains how Tensordyne combines power-efficient logarithmic math with a …
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Tensordyne co-founder and CPO R K Anand joins Austin to discuss the company's strategy for disrupting AI inference. RK explains how Tensordyne combines power-efficient logarithmic math with a battle-hardened networking fabric from partner HPE Juniper. The result is a high-density, air-cooled system designed to efficiently run massive Mixture-of-Experts models in existing data centers.
Key Takeaways:
- The core innovation isn't just log math, it's the patented method for accumulation. This turns expensive multiplications into cheap additions, freeing die space for a massive on-chip SRAM cache.- Networking is a partnership, not a project. Tensordyne leverages HPE Juniper's 7th-gen router fabric, skipping development cycles to get a 1-2 microsecond latency solution ideal for random MoE traffic.
- The power and density claims are radical. By combining log math silicon with an air-cooled fabric, Tensordyne packs 72 chips into a 13U chassis at just 30 kW — a quarter of the space and power of an NVL72.
- One go-to-market advantage is air cooling. The 30 kW, 19-inch rack system can be deployed in existing 'brownfield' enterprise and telco data centers that cannot support liquid cooling.
- Partnerships de-risk the aggressive timeline. Broadcom provides access to TSMC 3nm and HBM, while strategic investor HPE Juniper provides the carrier-grade fabric with 'five nines' reliability.
Chapters:
0:00 Introducing Tensordyne
5:32 The Juniper vs. Cisco Playbook
11:29 Origin Story: Automotive Power Constraints
15:37 The Secret Sauce of Log Math
18:02 Pivoting to the Data Center
22:08 Leveraging a Router Backplane for AI
27:22 Why Router Fabrics Suit MoE Models
34:12 The Three Phases of Inference Hardware
37:40 How One Chip Handles Pre-fill & Decode
40:34 The 'Too Good to Be True' System Specs
43:31 Go-to-Market: The Air-Cooled Advantage
48:21 De-risking with Strategic Partnerships
52:37 Solving the Software Problem with AIFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/- The software moat is eroding. Tensordyne argues that modern agentic AI workflows can now automate the generation of optimized software kernels, solving the classic adoption problem for new hardware.
NEWS TAKE: China's Optical Ban, Volta's $10B Anthropic Deal, AMD's Earnings
Austin Lyons and Vik Sekar break down three stories that hit semis last week. They analyze a proposed US ban on Chinese optical transceivers that threatens to cut off 50% of the global supply, the market's …
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Austin Lyons and Vik Sekar break down three stories that hit semis last week. They analyze a proposed US ban on Chinese optical transceivers that threatens to cut off 50% of the global supply, the market's reaction to AMD's surprise $800M CapEx spend despite strong earnings, and how a new company called Volta Infrastructure landed a $10B compute deal with Anthropic by pioneering a new financial model for AI.
Key Takeaways:
- The proposed ban on Chinese optical transceivers is based on a flawed security rationale—the components are simple signal converters, not a meaningful vector for malware.
- A ban would be self-defeating, as it would cut off the ~50% of global transceiver supply assembled in China, creating the very data center disruption it claims to prevent.
- AMD's successful pivot to a data-center-first company (58% of revenue) is being scrutinized for its high CapEx—$800M vs an expected $200-300M—revealing the hidden costs of securing supply.
- Nvidia's use of on-chip SRAM for inference's decode phase highlights a strategic gap for AMD, which lacks a compelling SRAM-based solution to compete on disaggregated workloads.
- Volta Infrastructure's $10B deal with Anthropic is an innovation in finance, not tech; it applies low-cost 'infrastructure debt' to AI compute by framing clusters as predictable 'token factories'.
- The Volta deal was necessary because all existing CSP capacity is allocated; it acts as a 'clean balance sheet' SPV to secure low-cost debt for Anthropic's new, dedicated Nvidia capacity.
Chapters:
0:00 Intro: News Take Format
0:40 The China Optical Ban
4:02 A Flawed Security Rationale
11:30 Market & Supply Chain Impact
15:07 Investment Paralysis
15:52 AMD's Earnings Scrutiny
24:46 AMD's Missing SRAM Strategy
25:33 Volta's $10B Anthropic Deal
28:55 Volta's 'Toll Road' Model
32:19 Why the Volta Deal Was Necessary
33:38 The 'One Customer' Counterpoint
34:27 Wrap: Tech & Financial InnovationFollow Chipstrat:
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The physical limits of copper are forcing a shift to optical interconnects in AI data centers. Austin sits down with GlobalFoundries' Thomas Barber to unpack why GF thinks it can lead that transition twice …
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The physical limits of copper are forcing a shift to optical interconnects in AI data centers. Austin sits down with GlobalFoundries' Thomas Barber to unpack why GF thinks it can lead that transition twice over: once with its long-running silicon photonics platform, and again with the specialty Silicon Germanium process the industry needs to drive it.
"The enemy to me right now is copper. I'm trying to beat copper, right? If TSMC wins and we win, that's great because we're both displacing copper. And until all the copper is gone, there's plenty of market to go around."
— Thomas Barber, GlobalFoundriesKey Takeaways:
- Copper's usable range halves every time the data rate doubles, and 200 Gbps/lane inside a rack-scale AI cluster is already past the point copper can handle.- CPO's real win isn't speed, it's power: saving 20-25 pJ/bit frees part of a data center's fixed 50-100 MW budget to go toward compute instead of moving bits.
- GlobalFoundries leads photonics revenue for an unglamorous reason: it moved to 300mm wafers early, which yields 2.25x more die per wafer than the 200mm lines rivals still run.
- CPO can end up more reliable than the pluggables it's replacing, not less, because it deletes the physical plug connector, and dust at that connector is the leading cause of field failures.
- The OCI MSA picks NRZ over faster PAM4, deliberately going wide and slow, because NRZ's native bit error rate is a million times lower, which simplifies the receiver and cuts power.
- GlobalFoundries stacks two specialty processes into one edge: micro-mirror couplers on the photonic side, and Silicon Germanium transistors hitting 350-400 GHz on the electrical side driving them.
- The real competitor for silicon photonics isn't another foundry, it's copper itself — and that market is big enough that GlobalFoundries and TSMC can both win without taking share from each other.
Chapters:
0:00 GlobalFoundries in Photonics
1:21 GF's Photonics Strategy
3:02 GF's Market Leadership
5:06 300mm Wafer Advantage
6:55 Copper's Range Limits
9:18 Pluggable to CPO
13:48 CPO Reliability
19:22 OCI MSA Explained
26:20 GF's Scale Platform
29:04 Micro Mirror Technology
31:32 Photonics vs. Copper
38:25 Silicon Germanium AdvantageFollow Chipstrat:
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A retimer is a small, unglamorous chip. Astera turned it into a high-margin franchise. Austin and Vik cover why copper gives up at PCIe speeds, what a retimer does that a redriver can't, and how one H100 …
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A retimer is a small, unglamorous chip. Astera turned it into a high-margin franchise. Austin and Vik cover why copper gives up at PCIe speeds, what a retimer does that a redriver can't, and how one H100 socket became a moat. Then Scorpio: can Astera take switch share from Broadcom?
Key Takeaways:
- 30cm of PCB trace at Gen 5's 32 GT/s and the signal is gone. Signal integrity is an inside-the-server problem, not just a rack-to-rack one.
- Gen 6 swaps NRZ for PAM4. Four voltage levels instead of two — a third the eye height, ~9.5 dB of SNR gone.
- A redriver amplifies, noise included. A retimer recovers the clock and data, rebuilds the signal, and resets the jitter budget.
- Astera won H100 by shipping PCIe 5 retimers at volume first, then bundling COSMOS on top. The chip became a fleet telemetry sensor.
- Sticky socket: H100 carried straight into an Aries 6 design-in on Blackwell.
- Scorpio moves up the stack. Same signal conditioning IP, higher ASP, pointed at Broadcom's PCIe switch business.
- Astera granted Amazon a warrant — 3.26M shares at $142.82, vesting against up to $6.5B of purchases through 2033. Equity flowing to the customer, and it sizes the Scorpio P-Series commitment behind Trainium 2 and 3.
Chapters:
0:00 The Astera Labs Franchise
3:32 The PCIe Copper Problem
6:53 Signal Smearing and Jitter
11:52 Eye Diagrams Explained
14:59 Equalization: Fixing the Signal
23:52 Redriver vs. Retimer
29:30 How Astera Won Nvidia
35:22 The Blackwell Scare
38:50 Scorpio: Moving into Switches
42:52 The UALink vs. Ethernet Battle
45:58 Taurus and Leo Product Lines
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/News Take: Hyperscaler CDS, SK Hynix Earnings, China's DUV
Austin Lyons and Vik Sekar break down the market's recent volatility. They discuss the rising fear around hyperscaler debt, visible in credit default swap (CDS) premiums, and the counter-argument that GPU …
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Austin Lyons and Vik Sekar break down the market's recent volatility. They discuss the rising fear around hyperscaler debt, visible in credit default swap (CDS) premiums, and the counter-argument that GPU ROI is actually understated. They then analyze the paradox of SK Hynix's massive stock drop despite record growth, and explain why China's new DUV lithography tool makes 3D chip stacking essential to their strategy.
Key Takeaways:
* Hyperscaler debt fears are quantified by rising credit default swap (CDS) premiums, signaling investor nervousness that the AI CapEx firehose is shifting from cash flow to riskier debt.* The counter-take on debt is that hyperscalers are under-earning on GPU assets — as long-term contracts re-price to spot rates 2x higher, the hardware's ROI will justify the financing.
* SK Hynix's 20% stock drop despite 257% YoY revenue growth shows a market priced for perfection, where a small miss against consensus triggers a panic disconnected from fundamentals.
* The memory market paradox: commodity DRAM is currently more profitable than HBM because HBM's production is 3x less bit-efficient per wafer, consuming scarce supply while DRAM spot prices soar.
* China's reported immersion DUV breakthrough is equivalent to ASML's late 2000s-era technology, a step toward self-sufficiency but not a leap to the leading edge.
Chapters:
0:00 The Market Is Freaking Out
0:21 Hyperscaler Debt and Credit Default Swaps
3:56 The Counter-Take: Under-Earning on GPUs
6:18 SK Hynix: Record Growth, Market Carnage
8:10 The HBM vs. DRAM Profitability Paradox
10:35 Leverage, Retail, and Panic Selling
12:05 China's Immersion DUV Breakthrough
13:28 The Limits of DUV: 7nm and Multi-Patterning
14:14 Logic Folding and 3D Stacking
16:12 A Long Journey to Self-Sufficiency
17:05 Surviving Semiconductor CyclicalityFollow Semi Doped:
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X: https://x.com/vikramskrDatacenter Interconnects: Copper vs. Optics, Nvidia's 78-Layer PCB, Co-Packaged Optics (CPO)
Vik Sekar and Austin Lyons tackle the biggest bottleneck in inference: moving data. They break down the three tiers of datacenter networking — scale up, scale out, scale across — and the core engineering …
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Vik Sekar and Austin Lyons tackle the biggest bottleneck in inference: moving data. They break down the three tiers of datacenter networking — scale up, scale out, scale across — and the core engineering trade-off at each layer: copper vs. optics. Topics include Nvidia's extreme measures to keep scale-up fabric electrical (a 78-layer mid-plane PCB), why Co-Packaged Optics is the "holy grail" everyone wants and no one can ship, and the serviceability problem standing in its way.
Key Takeaways:
- A single 72-GPU scale-up rack needs 5,000+ cables spanning ~2 km — at that density, the power and cost of every connection becomes a system-level constraint, not an implementation detail.
- The scale-up rule is "copper when you can, optics when you must": each pluggable optical module adds ~30W, and with thousands of links in the fabric, that penalty compounds fast.
- Nvidia is pushing copper past its usual limits with a 78-layer mid-plane PCB — 3x+ the layer count of a typical complex board — specifically to avoid paying the optics power tax in its scale-up fabric.
- Scale-up isn't just a training problem. Frontier MoE models need 72-GPU domains to hit memory bandwidth targets, which pulls high-performance interconnect into the inference conversation.
- Scale-up has the highest connection density of the three tiers, making it the largest TAM and the sharpest three-way fight between NVLink, UA-Link, and Ethernet.
- Co-Packaged Optics could cut interconnect power by two-thirds — but a single failed laser could brick an entire multi-thousand-dollar GPU package, and that serviceability risk is what's keeping it on the roadmap instead of in racks.
Chapters:
0:00 The Biggest Problem in Computing
7:14 The Three Tiers of Networking
13:49 Scale Up: Copper vs. Optics
17:59 Front-End vs. Back-End Networks
22:12 The Physical Scale of Cabling
28:46 Nvidia's 78-Layer Mid-Plane
33:16 How Optical Transceivers Work
39:16 The Power Penalty of Pluggables
42:09 The Business of Speed Transitions
44:40 The Promise and Peril of CPO
51:45 The Holy Grail of NetworkingFollow Chipstrat:
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Get more of Austin and Vik daily, free: https://daily.semidoped.com/PicoJool's Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects
Al Yuen, CEO of PicoJool, talks with Austin about using VCSELs for scale-up optical interconnects in AI data centers. Al explains why gallium arsenide (GaAs) supply is unconstrained while indium phosphide (InP) …
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Al Yuen, CEO of PicoJool, talks with Austin about using VCSELs for scale-up optical interconnects in AI data centers. Al explains why gallium arsenide (GaAs) supply is unconstrained while indium phosphide (InP) is limited, and how PicoJool can leverage existing supply chains to ship in the millions per month. They cover the roadmap from 1.6T to 12.8T, the trade-offs among 8×200G, 16×100G, and 32×50G, and the push to train the next generation of photonics engineers.
- The spec that changed is error rate. AI needs error-free links (10⁻¹⁰–10⁻¹² vs Ethernet's old 10⁻⁶) because GPUs act as one system — one error stalls the whole job.
- Single-mode optics can't hit the volume. Built for ~100K city-to-city links; datacenters need millions/month — a 10–50× gap
- GaAs vs InP is the whole supply story. VCSELs run on unconstrained GaAs; single-mode on constrained InP. 1M units: 8–10 weeks vs a sold-out 8–18 months.
- One platform, three flavors to 1.6T: 8×200G "fast and narrow," 16×100G LPO low-power, 32×50G NRZ "slow and wide" — pick on power, cost, and BER.
- 12.8T needs no new tech — just more of the same: 64 channels (4×16 array in a finger-sized connector) × 200G, scaling channels, bi-di wavelengths, and lane speed.
- Capacity isn't the time consuming part — qualification is. WIN runs ~1,000 wafers/week at ~240K VCSELs each, so 1M units = ~10 wafers. The wait is tier-1 (>6 mo) and tier-2 (~3 mo) quals.
Chapters:
0:00 Meet Al Yuen and PicoJool
2:29 Inventing the active optical cable
5:03 Engineering mindset, copper limits
8:43 Why VCSELs
13:45 Scale-up and bit error rate
20:09 Unconstrained vs constrained supply
21:53 Indium phosphide bottleneck
25:49 VCSEL design and foundry handoff
31:59 Product road map, 200G launch
34:16 Path to 3.2T and 12.8T
40:10 Ordering a million VCSELs
45:10 Ramp timing and training new engineers
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Vik welcomes Val Bercovici from Weka to discuss the rapidly evolving landscape of AI memory and storage. Val explains how Weka's architecture leverages high-bandwidth networks to make storage faster than …
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Vik welcomes Val Bercovici from Weka to discuss the rapidly evolving landscape of AI memory and storage. Val explains how Weka's architecture leverages high-bandwidth networks to make storage faster than motherboard DRAM. They dive into KV cache optimizations, the future of NAND flash tiers, and the role of CXL in AI inference. The episode concludes with a look at predictive memory offloading and the AI flywheel.
Chapters:
0:00 Welcome Val Bercovici, Weka
1:59 Memory situation and model routing
3:50 KV cache offloading to CMX
6:10 Network faster than motherboard
13:10 Weka as AI memory infrastructure
14:45 Inference market is different
16:06 Memory hierarchy and KV cache
19:40 KV cache optimizations and demand
25:20 DeepSeek's cache read pricing
34:49 NAND flash tiers: SLC vs QLC
43:01 High Bandwidth Flash (HBF)
49:59 CXL versus other interconnects
Follow Chipstrat:
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Austin and Vik break down the current memory crisis, where AI demand is driving unprecedented profits for memory makers like Micron, while simultaneously causing inflation and price hikes for consumer …
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Austin and Vik break down the current memory crisis, where AI demand is driving unprecedented profits for memory makers like Micron, while simultaneously causing inflation and price hikes for consumer electronics. They discuss how even premium brands like Apple are struggling to secure supply, leading them to controversial suppliers. The hosts also explore the long-term implications of AI's insatiable memory appetite and its impact on both data center and consumer markets.
Chapters:
0:00 Memory crisis hits
1:20 AI impacting consumers
3:00 AI causing inflation
6:48 Consumer demand drop?
8:49 AI demand inelastic
10:56 Long-term memory outlook
11:02 GoPro's memory woes
12:24 Apple's pricing power
18:20 Apple seeks CXMT DRAM
21:38 Shrinkflation for phones
23:16 Korea's memory investment
26:10 Micron's killing profits
33:00 Why AI needs so much DRAM
40:27 Future of AI training
44:34 Cost-optimizing inference
Follow Chipstrat:
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Qualcomm flew Austin to New York for its investor day, where the communications company laid out a plan to make data center, automotive, and IoT two-thirds of its business by FY29. Austin was in the room and …
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Qualcomm flew Austin to New York for its investor day, where the communications company laid out a plan to make data center, automotive, and IoT two-thirds of its business by FY29. Austin was in the room and asked Cristiano Amon a question on the record. Vik watched the whole thing on YouTube. Together they break down what actually changed.
The technical centerpiece is High Bandwidth Compute (HBC): stacking LPDDR on top of logic to expose the whole face of the chip for interconnects, claiming up to 100x more lanes and a path around the HBM bandwidth bottleneck. Austin and Vik dig into what's really under that memory, why "no advanced packaging needed" just moves the hard problem somewhere worse, and how it compares to d-Matrix. And as Austin put it: don't let anyone tell you HBM is dead. MOAR memory.
Then the roadmap: the AI200/250/300 accelerators, the C1000 server CPU (5 GHz, 250+ cores, Meta as a customer), the Alphawave and Modular acquisitions, and Chris Lattner's Mojo.
The most interesting takeaway might not be the data center at all. Qualcomm's edge play — AI-defined vehicles, cars as token generators, and a $1T robotics opportunity by 2040 — could be where High Bandwidth Compute matters most.
Chapters:
0:00 Communications? That's just the start
4:08 Inside Qualcomm's investor day
9:16 Can Qualcomm build a data center business?
13:09 Disaggregated inference opens the door
17:57 High Bandwidth Compute: memory on the XPU
30:29 "No advanced packaging" just moves the problem
36:20 The roadmap, Alphawave, and Modular
46:00 The C1000 CPU and the agentic shortage
50:40 Cars as token generators, the $1T robotics bet
57:32 The memory market: MOARFollow Semi Doped:
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Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.comAdvanced Packaging, TSMC CoWoS, Intel EMIB
New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB.Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.Three CoWOS …
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New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB.
Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.
- Three CoWOS flavors: silicon, organic RDL, local bridges
- EMIB embeds tiny bridges into the substrate, no interposer
- EMIB-T and EMIB-M add through-silicon vias and power capacitors
- Google is booking 3M TPUs on EMIB via MediaTek by 2028
- Package sizes keep climbing: 5.5x reticle today, 40x ahead
This episode is brought to you by SambaNova. Try SambaNova's fast inference today at the SambaNova Dashboard!
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.com
Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.comChapters:
(0:00) "There Is No Chip Without the Packaging"
(0:28) Intro and SpaceX IPO Day
(5:15) What We're Covering: CoWOS, EMIB, Google
(7:40) Simple Packaging: Wire Bonds to Flip Chip
(17:07) What Makes Packaging "Advanced"
(33:44) CoWOS: Three Flavors Explained
(45:30) EMIB: Intel's Embedded Bridge Approach
(52:47) EMIB-T and EMIB-M
(57:31) CoWOS vs. EMIB Trade-offs
(1:02:18) Google's 3M TPU EMIB OrderComputex Mania 2026: Optics and Power
Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together. They share insights about the massive show, the people they …
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Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together.
They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology.
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.com
Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com
Chapters
00:00 Meeting in Person for the First Time
03:05 Experiencing Computex: A Massive Show
05:17 Connecting with the Audience: Real-Life Encounters
06:46 Networking with Industry Leaders
10:42 Keynote Highlights: Marvell's Vision
15:11 The Future of Interconnects: CPO and Beyond
22:54 Exploring Optical Interconnects and Future Technologies
25:56 Micro LED Developments and Future Conferences
27:34 Power Innovations in Data Centers
30:54 Intel's Keynote and New CPU Technologies
36:31 Intel Foundry's Advancements and Industry ImplicationsHuawei's Tau Scaling Law: Is the "EUV Killer" Real?
Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack …
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Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards.
They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.
The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.
Chapters:
0:00 The "EUV killer" paper that broke the internet
2:28 What Huawei actually announced at ISCAS
4:00 Tau scaling: optimize delay, not transistors
8:58 The equation and the 10x AI claim
11:05 Logic folding: stacking logic on logic
17:24 Who builds it, and can hybrid bonding be banned?
24:16 Why this is bullish for ASML
29:49 The other tau knobs: memory and optics
35:18 Takeaways: packaging, EDA, multiphysics
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X: https://x.com/vikramskrLithography Masterclass
Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few …
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Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few companies can afford to.
The thread is economics. An EUV machine runs about $400 million, a new fab needs roughly 15 of them, and the total bill clears $20-30 billion before a single wafer ships. Austin and Vik trace the whole story: Rock's Law and the cost of a fab, what it actually takes to build one, the evolution from 193nm DUV through multi-patterning to 13.5nm EUV, how ASML generates EUV light by exploding falling tin droplets, and the move to high NA and its mirrors. Along the way, the fun history — i-line, krypton fluoride, immersion lithography, and the engineer who started it all by flipping a microscope upside down.
Then the part that matters most: where lithography goes next. Two startups, xLight and Substrate, are attacking the cost problem from first principles. xLight wants to decouple the light source from the scanner with a free-electron laser and sell photons as a service. Substrate wants to skip EUV entirely and revive X-ray lithography. If either works, the economics of who can build a fab change completely.
Chapters:
0:00 The 13F panic, and today's topic
2:23 Why the real story is economics, not physics
6:18 Austin in the clean room: graphene and bunny suits
10:06 Rock's Law and the $20 billion fab
18:08 DUV, the Sharpie, and a history of light
24:58 Multi-patterning, explained with a football field
34:45 How EUV makes 13.5nm light from tin droplets
41:14 High NA, anamorphic optics, and the half-field tax
46:45 The startups rethinking lithography: xLight and SubstrateRelevant reading:
Chipstrat — The economics of lithography: https://www.chipstrat.com/p/lithography-economics
Chipstrat — xLight and photons as a service: https://www.chipstrat.com/p/photons-as-a-service
Chipstrat — Substrate and X-ray lithography: https://www.chipstrat.com/p/substrate
Vik's Newsletter — the viability of X-ray lithography: https://www.viksnewsletter.com/p/an-in-depth-look-at-the-viability
Fred Chen — LELE multipatterning and EUV stochastics (Substack): https://frederickchen.substack.com/p/can-lele-multipatterning-help-against
Chip War, Chris Miller
Focus, Marc Hijink (the ASML book): https://www.amazon.com/Focus-Inside-struggle-complex-machine-ebook/dp/B0CW1FLCD4Follow Chipstrat:
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